1. Field of the Invention
The present invention generally relates to so-called fin field effect transistors (FET) integrated in a full complementary metal-oxide-semiconductor (CMOS) device process flow. More particularly this invention relates to the integration in such a full CMOS process flow of n-type FinFETs and/or p-type FinFETs having a channel length of about 100 nanometer or less.
2. Description of the Related Technology
Today's state-of-the-art semiconductor chips feature technology nodes of 0.18 micron (180 nanometers) with 0.13 micron (130 nanometers) technologies just beginning to reach the marketplace. Now the industry plans to deliver 90 nanometers in 2004, 65 nanometers in 2007, 45 nanometers in 2010, 32 nanometers in 2013 and 22 nanometers in 2016. This 2001 schedule, as set forward in the International Technology Roadmap for Semiconductors (ITRS) defined by the Semiconductor Industry Association (SIA), translates to smaller chip dimensions earlier in time than previously thought. Among the main transistor scaling issues to be solved are the need for thinner gate oxides resulting in a higher on-current and hence increased switching speed, a smaller off-current and lower threshold voltage to allow such gate oxide scaling and the use of lower supply voltages, a higher channel mobility and smaller series resistance of the source/drain regions. In order to meet the stringent scaling requirements of this forecast, non-classical CMOS devices and novel materials, such as metal gate materials and high-k gate dielectrics, are currently under investigation.
One of these non-classical CMOS devices is the so-called FinFET, where the gate envelops at least partially the channel region, contrary to the classic planar device where the gate electrode is formed in one plane on top of the channel region, which is part of the substrate. This substrate further comprises the source and drain regions adjacent to the channel region. The idea of making a double gate transistor by using the sidewalls of a dry-etched silicon (Si) fin as conducting channels was published in 1998 by D. Hisamoto et al. in “A folded-channel MOSFET for deep-sub-tenth Micron Era” in the IEDM Technical Digest 1998 pp 1032–1034. In the Fin FET a thin gate line straddled a thin silicon channel fin. The fabrication process was not optimized and was meant solely for single device demonstration. The proposed process included the use of inside spacers, which could decrease the gate length beyond the lithographical limits. However, the process had some severe drawbacks. It didn't allow the manufacturing of CMOS devices because poly SiGe was used to form the source/drain regions for the pMOS device while poly Si was used to form the source/drain regions of the nMOS device. The final device was assembled by subsequently forming the fin channel, the gate and the source/drain regions. The source/drain areas were not aligned to the gate. The proposed process also didn't allow the integration of SOI CMOS FinFET with SOI BiCMOS.
Other fabrication processes, reported in literature, include many variations of one basic fabrication process called the “quasi planar” FinFET. Choi et al describe such an alternative in “sub 20-nm CMOS FinFET technologies”, IEDM Technical Digest 2001, pp 421–424. This alternative is based on “spacer” lithography: the pattern of the masking Phosphorous-doped Silicon Glass (PSG) spacers is transferred to the underlying Silicon-On-Insulator (SOI) layer thereby having the width of the silicon fins corresponding to the width of the masking spacers. The process only allows submicron fins with a single width as determined by the PSG layer thickness. In this underlying silicon layer source/drain regions can be patterned using conventional lithographic processing. Instead of using this “spacer” lithography alternatives are known using e-beam lithography to pattern the silicon fin channels. Such a FinFET device is described in details in “High-performance symmetric-gate and CMOS compatible Vt asymmetric-gate FinFET devices” in IEDM technical digest 2001 pp 437–440, by J. Kedzierski et al. An example of such a device is reproduced in the following drawings, wherein the source/drain regions or pads, as they are labeled there, are formed together with the fin channel in the SOI layer using optical lithography and a hard mask trimming technique. These “quasi planar” FinFET type of processes could allow the formation of CMOS devices. In most alternatives the source/drain areas are not aligned to the gate. As all the silicon of the SOI layer outside the source/drain pads and the fin area is removed, the devices are reciprocally insulated afterwards by forming a planarized oxide layer over the individual devices. The leakage at the edges of this mesa isolation however might degrade device performance. These “quasi planar” FinFET type of processes don't allow the incorporation of metal gates and high-k gate dielectrics easily. Especially the use of metal gates is important for CMOS devices since tuning of the gate workfunction by choosing the appropriate gate electrode material is probably the only way to tune the threshold voltage and thus the device performance.
In U.S. Pat. No. 6,252,284, a planarized fin device is disclosed. The inventors propose a complex process schema comprising the steps of first forming the fin, polishing the fin until its desired height is reached, depositing and patterning the gate dielectric and electrode as to cross the fin, forming a silicide on the exposed regions of the fin, forming source/drain areas by depositing a polysilicon layer over the crossing of fin and gate and polishing this deposited polysilicon layer down to the level of the gate electrode followed by an etch-back of the polished polysilicon layer below the level of the gate electrode, forming a silicide on the exposed surface of the gate electrode. The proposed process flow is very unlikely to be combinable with classical CMOS processing as it requires a large number of additional process steps in an order that is at some points reverse to classical CMOS processing.
In U.S. Pat. No. 6,118,161, an alternative process to form a FinFET is disclosed. The inventors use the same nitride hard mask to define in a first patterning step the mesa active areas (132) in an SOI layer (106) and to define in a second patterning step a disposable gate pattern (134) aligned to and within the active area (132). Source and drain area's are defined aligned to this disposable gate pattern. The substrate is covered with an insulating layer (114) being planarized to expose the disposable gate pattern. A slot pattern (136) is etched in this disposable gate pattern and this slot pattern is then used as a hardmask to form channel strips (108) between source and drain. The proposed method doesn't offer an efficient electrical insulation in between the active area's or between the gate and the source/drain regions.